What setup does REP do?

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  1. What is the best way to set a register to zero in x86 assembly: xor, mov or and?
  2. Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
  3. Enhanced REP MOVSB for memcpy
  4. How many CPU cycles are needed for each assembly instruction?
  5. Adding a redundant assignment speeds up code when compiled without optimization
  6. Is performance reduced when executing loops whose uop count is not a multiple of processor width?
  7. Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
  8. How are x86 uops scheduled, exactly?
  9. Why does breaking the “output dependency” of LZCNT matter?
  10. What methods can be used to efficiently extend instruction length on modern x86?
  11. 32-byte aligned routine does not fit the uops cache
  12. Is ADD 1 really faster than INC ? x86 [duplicate]
  13. Size of store buffers on Intel hardware? What exactly is a store buffer?
  14. Why is a conditional move not vulnerable to Branch Prediction Failure?
  15. Can modern x86 implementations store-forward from more than one prior store?
  16. Assembly – How to score a CPU instruction by latency and throughput
  17. Unexpectedly poor and weirdly bimodal performance for store loop on Intel Skylake
  18. Relative performance of x86 inc vs. add instruction
  19. How can the rep stosb instruction execute faster than the equivalent loop?
  20. Why are loops always compiled into “do…while” style (tail jump)?
  21. Why does C++ code for testing the Collatz conjecture run faster than hand-written assembly?
  22. Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?
  23. Is there a penalty when base+offset is in a different page than the base?
  24. What is the purpose of the EBP frame pointer register?
  25. Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
  26. Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
  27. Is it safe to read past the end of a buffer within the same page on x86 and x64?
  28. Are there any modern CPUs where a cached byte store is actually slower than a word store?
  29. Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
  30. Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?

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