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- Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
- How many CPU cycles are needed for each assembly instruction?
- Adding a redundant assignment speeds up code when compiled without optimization
- Is performance reduced when executing loops whose uop count is not a multiple of processor width?
- Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
- Why does breaking the “output dependency” of LZCNT matter?
- What setup does REP do?
- 32-byte aligned routine does not fit the uops cache
- Size of store buffers on Intel hardware? What exactly is a store buffer?
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- INC instruction vs ADD 1: Does it matter?
- Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?
- Is there a penalty when base+offset is in a different page than the base?
- What is the purpose of the EBP frame pointer register?
- What happens after a L2 TLB miss?
- Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
- Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
- What methods can be used to efficiently extend instruction length on modern x86?
- Are there any modern CPUs where a cached byte store is actually slower than a word store?
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- Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
- Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
- Can modern x86 implementations store-forward from more than one prior store?
- Unexpectedly poor and weirdly bimodal performance for store loop on Intel Skylake
- Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
- Modern x86 cost model
- Cycles/cost for L1 Cache hit vs. Register on x86?
- Relative performance of x86 inc vs. add instruction
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