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- What is the best way to set a register to zero in x86 assembly: xor, mov or and?
- What methods can be used to efficiently extend instruction length on modern x86?
- What setup does REP do?
- Is ADD 1 really faster than INC ? x86 [duplicate]
- Can modern x86 implementations store-forward from more than one prior store?
- Relative performance of x86 inc vs. add instruction
- How can the rep stosb instruction execute faster than the equivalent loop?
- Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
- Why are loops always compiled into “do…while” style (tail jump)?
- Why does C++ code for testing the Collatz conjecture run faster than hand-written assembly?
- Enhanced REP MOVSB for memcpy
- INC instruction vs ADD 1: Does it matter?
- How many CPU cycles are needed for each assembly instruction?
- Adding a redundant assignment speeds up code when compiled without optimization
- Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
- Why does breaking the “output dependency” of LZCNT matter?
- Is there a penalty when base+offset is in a different page than the base?
- What is the purpose of the EBP frame pointer register?
- Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
- Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
- Is it safe to read past the end of a buffer within the same page on x86 and x64?
- 32-byte aligned routine does not fit the uops cache
- Size of store buffers on Intel hardware? What exactly is a store buffer?
- Why is SSE scalar sqrt(x) slower than rsqrt(x) * x?
- Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
- Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
- Assembly – How to score a CPU instruction by latency and throughput
- Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
- Performance optimisations of x86-64 assembly – Alignment and branch prediction
- Modern x86 cost model