Modern x86 cost model

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The best reference is the Intel Optimization Manual, which provides fairly detailed information on architectural hazards and instruction latencies for all recent Intel cores, as well as a good number of optimization examples.

Another excellent reference is Agner Fog’s optimization resources, which have the virtue of also covering AMD cores.

Note that specific cost models are, by nature, micro-architecture specific. There’s no such thing as an “x86 cost model” that has any kind of real validity. At the instruction level, the performance characteristics of Atom are wildly different from i7.

I would also note that memory accesses and branches are not actually “cheap” on x86 cores — it’s just that the out-of-order execution model has become so sophisticated that it can successfully hide the cost of them in many simple scenarios.

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